This invention relates to semiconductor processing of integrated circuit (IC) structures. More particularly, the present invention relates to processes using damascene (or in-laid) metallization to form a capacitor between metal interconnect layers of an IC.
In a typical integrated circuit (IC), multiple metal interconnect layers overlay the substrate and the circuit elements constructed thereon. The metal interconnect layers are separated from each other and from the substrate by dielectric layers. Each metal interconnect layer is formed into individual patterns of metal traces, or interconnects, that electrically connect the various circuit elements of the IC. Also, other circuit elements, such as capacitors, can be formed between the metal interconnect layers to relieve space constraints at the substrate level and to improve performance of these elements.
A common technique for forming the metal interconnects involves depositing a film of the metal material onto the top surface of the IC (typically a dielectric layer) and etching away the undesired areas of this film to form the pattern. This technique can also be used to form the capacitors between the metal interconnect layers.
Another way to form the metal interconnects involves etching the pattern into the dielectric layer to form trenches in the dielectric layer and then depositing the metal over the dielectric layer and into the trenches. The metal is then removed with a chemical mechanical polishing (CMP) or etching process back to the dielectric layer, leaving the metal in the trenches in the patterns of the metal interconnects. This second method is known as a xe2x80x9cdamascene process.xe2x80x9d Via connections between the metal interconnect layers and the substrate structures may also be formed by damascene metallization processes. In fact, the via connections and the overlying metal interconnects can be formed in the same damascene process, called a xe2x80x9cdual damascenexe2x80x9d process.
Damascene metallization processes for forming the metal interconnect layers have gained in popularity over the metal deposition and etching types of processes described briefly above. The popularity is due in part to the fact that the CMP processes commonly used at the end of the damascene process create a fairly smooth surface upon which the next layers can be formed. The damascene processes can also avoid some of the complications of metal etching which have occurred as geometries of the structures (i.e. electrical elements and conductors) have been made smaller in width. For example, to construct metal elements or conductors of the same resistance or conductance as prior elements, but with a narrower width, the height must be made greater for a greater aspect ratio. To do so using metal etching processes requires that the metal be deposited in a relatively thick layer and then etched to form relatively tall and narrow structures with small gaps in between that are then filled with insulating material. It has proven very difficult, however, to use such techniques to form the tall, narrow, closely-spaced metal structures and then fill in the gaps. Damascene processes, on the other hand, have been proven to be able to form the necessary deep, narrow, closely-spaced trenches and to fill the trenches with the metal material to form the desired metal elements and conductors.
Due to the increasing popularity of damascene metallization, it has become desirable to form the capacitors between the metal interconnect layers using the damascene processes. The capacitor formation processes, however, are typically complex and require considerable extra steps to perform. Also, the capacitor structures formed thereby have complex patterns, which require stringent process controls.
It is with respect to these and other background considerations that the present invention has evolved.
The present invention forms a vertical metal-insulator-metal (VMIM) capacitor between metal interconnect layers of an integrated circuit (IC). The technique for forming the capacitor utilizes damascene processes to form a simple vertical capacitor structure with a minimum of additional process steps beyond those needed to form the metal interconnects. The plates of the capacitor are formed using the same damascene processes used to form the metal interconnects in the interconnect layers and the via connections therebetween. In this manner, the VMIM capacitor is formed with a deposited dielectric as the insulator between the capacitor plates.
These and other improvements are achieved in a method of forming a VMIM capacitor in an interlayer dielectric (ILD) layer between upper and lower metal interconnect layers in an integrated circuit (IC), the lower metal interconnect layer being separated from a substrate of the IC by at least one dielectric layer or another underlying metal interconnect layer. The upper metal interconnect layer is formed by a damascene metallization process in a top side of the ILD layer along with a first vertical capacitor plate. The first vertical capacitor plate of the VMIM capacitor is formed in the upper metal interconnect layer and the ILD layer by the same damascene metallization process that forms the upper metal interconnect layer. A capacitor dielectric material is formed or deposited onto a vertical sidewall of the vertical capacitor plate. A second vertical capacitor plate is formed by another damascene metallization process adjacent to the capacitor dielectric material. In this manner, the VMIM capacitor is formed with two vertical capacitor plates and the capacitor dielectric therebetween using the same or similar damascene metallization process steps used to form the metal interconnect layers.
The method preferably also includes exposing a vertical sidewall of the first vertical capacitor plate by forming a trench in the ILD layer adjacent to the first vertical capacitor plate. A metal liner is then preferably formed on the inner bottom and sidewall surfaces of the trench, including on the exposed vertical sidewall of the first capacitor plate. The metal liner thus forms an extension of the first vertical capacitor plate as an outer capacitor plate of the VMIM capacitor at least partially surrounding the second, or inner, vertical capacitor plate with the capacitor dielectric material therebetween. Alternatively, the method includes forming the first vertical capacitor plate and a third vertical capacitor plate on opposite sides of the second vertical capacitor plate and electrically connecting the first and third vertical capacitor plates together to form an outer capacitor plate of the VMIM capacitor. Additionally, the method preferably forms one or more metal conductor lines in the upper metal interconnect layer and one or more via connections through the ILD layer, such that the metal conductor line(s) and the via connection(s) form the first (and third, if present) vertical capacitor plate(s) of the VMIM capacitor.
The method also preferably forms a bottom capacitor plate for the VMIM capacitor below the second vertical capacitor plate with the capacitor dielectric material therebetween. In this embodiment, it is further preferable to form a bottom capacitor plate within the lower metal interconnect layer. Alternatively, the method preferably removes the portion of the lower metal interconnect layer that is below the region occupied by the second vertical capacitor plate, when it is desired to ensure that there is no bottom capacitance.
The method also preferably forms another capacitor structure, similar to the one described above, but disposed in another ILD layer and metal interconnect layer above the previously mentioned ILD layer and upper metal interconnect layer. Corresponding capacitor plates in the two capacitor structures are electrically connected together to form two larger stacked capacitor plates for the VMIM capacitor. An additional ILD layer and metal interconnect layer are preferably interposed between the two capacitor structures to provide electrical connections through the additional metal interconnect layer between the corresponding capacitor plates of the upper and lower capacitor structures.
Alternatively, another capacitor structure is formed, similar to the one described above and disposed in the same ILD layer and metal interconnect layer, but located beside the first capacitor structure. Corresponding capacitor plates of the two capacitor structures are preferably electrically connected together to form two larger capacitor plates for the VMIM capacitor.
The previously mentioned and other improvements are also achieved in a VMIM capacitor in an IC. The IC has a substrate, a lower metal interconnect layer and an upper damascene-metallization interconnect layer. The lower metal interconnect layer and the substrate are separated by a dielectric layer, and the lower metal interconnect layer and the damascene-metallization interconnect layer are separated by an ILD layer. The VMIM capacitor comprises two vertical capacitor plates and a capacitor dielectric between the two vertical capacitor plates. The two vertical capacitor plates are formed by damascene metallization processes. One of the vertical capacitor plates is formed at least partially by the same damascene metallization process used to form the upper damascene-metallization interconnect layer. Both vertical capacitor plates are disposed within the upper damascene-metallization interconnect layer and at least partially through the ILD layer.
It is preferable that the VMIM capacitor also comprise a metal conductor line within the upper damascene-metallization interconnect layer and a via connection extending between the two interconnect layers. In this manner, the conductor line and the via connection define at least a portion of the first vertical capacitor plate.
It is also preferable that the VMIM capacitor further comprise the inner and outer vertical capacitor plates. The outer capacitor plate preferably includes the first vertical capacitor plate and also preferably an additional (third) vertical capacitor plate disposed on an opposite side of the second (inner) vertical capacitor plate from the first vertical capacitor plate. The first and third vertical capacitor plates are electrically connected together. Thus, the outer vertical capacitor plate at least partially surrounds the inner vertical capacitor plate.
The VMIM capacitor preferably further comprises a metal liner that at least partially surrounds the capacitor dielectric and second vertical capacitor plate. The metal liner also preferably electrically connects to the first vertical capacitor plate to form an extension of the first vertical capacitor plate as an outer capacitor plate.
The VMIM capacitor preferably further comprises a bottom capacitor plate below the second vertical capacitor plate and electrically connected to the first vertical capacitor plate. The bottom capacitor plate also preferably is integrated in metal conductor lines in the lower metal interconnect layer. Alternatively, in order to avoid undesired bottom capacitance, any metal conductor lines in the lower metal interconnect layer are preferably excluded from the region below the second vertical capacitor plate.
The VMIM capacitor also preferably comprises a stacked capacitor configuration, wherein a second capacitor structure, similar to the capacitor structure described above, is formed in an additional ILD layer and additional upper damascene-metallization interconnect layer above the aforementioned ILD layer and upper damascene-metallization interconnect layer. Corresponding capacitor plates in the two capacitor structures are electrically connected together to form a larger stacked capacitor. Alternatively, the VMIM capacitor preferably comprises a side-by-side capacitor configuration, wherein a second capacitor structure, similar to the capacitor structure described above, is formed in the same ILD layer and upper damascene-metallization interconnect layer in which the first capacitor structure is formed, but laterally spaced from the first capacitor structure. Corresponding capacitor plates in the two capacitor structures are electrically connected together to form a larger side-by-side capacitor.
A more complete appreciation of the present invention and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments of the invention taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.